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Honored Contributor
Honored ContributorProblem Vhdl the process with Reset option
I have written VHDL code for VGA controller for spartan 3E board. The code simulates and works well without the reset and clk process in the code below. But after inserting the process(reset,clk) the...
Altera_ForumHonored Contributor
Honored ContributorI think Altera coding style book on altera litterature web gives good advices. http://www.altera.com/education/training/courses/ohdl1110?gsa_pos=2&wt.oss_r=1&wt.oss=vhdl and others
On http://www.doulos.com/ keep in mind that vhdl is a description langage (not a programming langage) For example, in you first post, you tried to connect 2 outputs together. For an hardware designer, it is prohibited except for tri-state, open drain...
