Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorProblem Vhdl the process with Reset option
I have written VHDL code for VGA controller for spartan 3E board. The code simulates and works well without the reset and clk process in the code below. But after inserting the process(reset,clk) the...
Altera_ForumHonored Contributor
Honored ContributorHi,
you can not drive h_count/v_count in two different processes. This will result in an undefined value (as you can see in your simulation). You should use something like that : process(clk,reset) begin if reset = '1' then h_count <= (others => '0'); elsif (clk'event and clk = '1') then .. Regards, HJS
