Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Problem Vhdl the process with Reset option

I have written VHDL code for VGA controller for spartan 3E board. The code simulates and works well without the reset and clk process in the code below. But after inserting the process(reset,clk) the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

@wolforth

If i change the code as you said it works, But if i replace the first process by this one

process(reset)

begin

if reset = '1' then

h_count <= (others => '0');

v_count <= (others => '0');

video_on <= '0';

end if;

end process;

It doesn't work. Why? I tried to find a book that would clearly address these issues but couldn't find any. Can you suggest any solid book?

Thank you