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Altera_Forum
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15 years ago

Problem using DDR3 bottom port with StratixIV EP4SGX230KF40C2

Hi, I'm trying to introduce with SOPC_BUILDER the DDR3 64 bits in my design, that also includes NIOS 2 and flash. Analysis and synthesis go well, but when I try to run the hello_world test on...
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Altera_Forum
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15 years ago

Hi Nekojiru,

I compared the DDR3 configuration values with those on the BTS design and I actually found a few differences: after some tuning now the memory is readable and the hello_world works!

Thank you for your help!

ALA