Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Problem using DDR3 bottom port with StratixIV EP4SGX230KF40C2

Hi, I'm trying to introduce with SOPC_BUILDER the DDR3 64 bits in my design, that also includes NIOS 2 and flash. Analysis and synthesis go well, but when I try to run the hello_world test on...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi there!

I added the onchip mem and ran the program from there (all the elf section on the onchip, as well as stack, heap, exeption vector) keeping the ddr3 bottom untouched: I CAN see the hello world print, that is everything works if I do not use the ddr3 bottom.

If the program (or some routine, as in the case the exception vector is located on ddr3) tries to access that memory the program stalls.

If it's not a problem of memory configuration in SOPC, I can also think about a wrong interaction between ddr3 and NIOS SBT, but where?

Let me remind that I have no problem with the ddr3 top...

Please, help!

ALA