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Altera_Forum
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15 years ago

Problem using DDR3 bottom port with StratixIV EP4SGX230KF40C2

Hi, I'm trying to introduce with SOPC_BUILDER the DDR3 64 bits in my design, that also includes NIOS 2 and flash. Analysis and synthesis go well, but when I try to run the hello_world test on...
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Altera_Forum
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15 years ago

You might want to distinguish the issue from DDR.

I feel like that is just a SBT issue.

Try building simple design, which only contains, CPU, OnChipMem, and jtag-uart.

If you can not see any hello world, then it is tool or software issue.

The other way is to use LED if the program is really working even though no-output.

You can write very simple design that on/off LED from software, so you won't see any command line response, but at least you can confirm that the software is running properly in FPGA.