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Altera_Forum
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15 years ago

Problem using DDR3 bottom port with StratixIV EP4SGX230KF40C2

Hi, I'm trying to introduce with SOPC_BUILDER the DDR3 64 bits in my design, that also includes NIOS 2 and flash. Analysis and synthesis go well, but when I try to run the hello_world test on...
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Altera_Forum
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15 years ago

Hi nekojiru,

thanks for the suggestion, I removed the unused uart, unfortunately nothing has changed, hello_world doesn't work yet.

I also tried to use both the top (16bits) and bottom(64bits) and on this system we ran a memory_test example on NIOS from the ddr3_top (I mean all the elf sections and stack and heap on the ddr3_top) trying accessing memory locations on the ddr3_bot. In this case the program starts but stalls when accessing any ddr3_bot location.

I'm still suspecting some mis-configuration of the memory controller or something related to the clock phase, but everything seems ok.

Any idea?

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Which Quartus version are you using?

I see you have 2 uart(s) in a SOPC.

As far as I recall, there was an issue that the SBT will mess up with multiple connection points in Q10.0. It seems like OK in 10.1.

If you remove one of the uart, it may work.

https://www.alteraforum.com/forum/attachment.php?attachmentid=3641

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