Forum Discussion
Altera_Forum
Honored Contributor
14 years agoThe select line is sampled on the rising edge of the clock. So if sel = 0 then output = A, sel = 1 output = B.
if you tied clock and select together, on the rising edge of clock, select would also be changing, and so you would have no garantee of A or B - you might even make it go meta-stable. And another point - you can only use a single clock edge inside an FPGA