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Altera_Forum
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11 years ago

problem in interfacing

Hi all, can any one suggest me how to interface altera cyclone 3 fpga starter kit( EP3C25F324 ) and ti daughter card ( SDALTEVK/NOPB ). i have both boards. when i see both schematic diagram the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

i give you full detail of pin location, for your more understanding.

altera_reserved_tck Input 2.5 V (default) 8mA (default)

altera_reserved_tdi Input 2.5 V (default) 8mA (default)

altera_reserved_tdo Output 2.5 V (default) 8mA (default) 2 (default)

altera_reserved_tms Input 2.5 V (default) 8mA (default)

clkin_50 Input PIN_A9 8 B8_N0 1.8 V 8mA (default)

CLKOUT_SMA Output PIN_A1 8 B8_N0 1.8 V 8mA (default) 2 (default)

DIPSW[7] Input PIN_H15 6 B6_N0 2.5 V 8mA (default)

DIPSW[6] Input PIN_D17 6 B6_N0 2.5 V 8mA (default)

DIPSW[5] Input PIN_H13 6 B6_N0 2.5 V 8mA (default)

DIPSW[4] Input PIN_D18 6 B6_N0 2.5 V 8mA (default)

DIPSW[3] Input PIN_C17 6 B6_N0 2.5 V 8mA (default)

DIPSW[2] Input PIN_M5 2 B2_N0 2.5 V 8mA (default)

DIPSW[1] Input PIN_P18 5 B5_N0 2.5 V 8mA (default)

DIPSW[0] Input PIN_R16 5 B5_N0 2.5 V 8mA (default)

freerun Output PIN_T17 5 B5_N0 2.5 V (default) 8mA (default) 2 (default)

genlock_no_lock Input PIN_M6 3 B3_N0 2.5 V 8mA (default)

genlock_no_ref Input PIN_M13 4 B4_N0 1.8 V 8mA (default)

hsync_n Input PIN_E1 1 B1_N0 1.8 V 8mA (default) 0 MHz

hsync_p Input PIN_E2 1 B1_N0 2.5 V 8mA (default) 0 MHz

I2C_SCL Bidir PIN_N16 5 B5_N0 2.5 V (default) 8mA (default) 2 (default)

LED[7] Output PIN_E9 8 B8_N0 1.8 V 8mA (default) 2 (default)

LED[6] Output PIN_C9 8 B8_N0 1.8 V 8mA (default) 2 (default)

LED[5] Output PIN_E10 8 B8_N0 1.8 V 8mA (default) 2 (default)

LED[4] Output PIN_D9 8 B8_N0 1.8 V 8mA (default) 2 (default)

LED[3] Output PIN_N9 3 B3_N0 1.8 V 8mA (default) 2 (default)

LED[2] Output PIN_N12 4 B4_N0 1.8 V 8mA (default) 2 (default)

LED[1] Output PIN_P12 4 B4_N0 1.8 V 8mA (default) 2 (default)

LED[0] Output PIN_P13 4 B4_N0 1.8 V 8mA (default) 2 (default)

oddeven_n Input PIN_L18 5 B5_N0 2.5 V (default) 8mA (default)

oddeven_p Input PIN_K18 5 B5_N0 2.5 V (default) 8mA (default)

PBSW[3] Input PIN_B10 7 B7_N0 1.8 V 8mA (default)

PBSW[2] Input PIN_A10 7 B7_N0 1.8 V 8mA (default)

PBSW[1] Input PIN_F2 1 B1_N0 2.5 V 8mA (default)

PBSW[0] Input PIN_F1 1 B1_N0 2.5 V 8mA (default)

pll_clk_n Input PIN_F18 6 B6_N0 2.5 V (default) 8mA (default)

pll_clk_p Input PIN_F17 6 B6_N0 2.5 V (default) 8mA (default)

PLL_SDA Bidir PIN_N11 4 B4_N0 1.8 V 8mA (default) 2 (default)

rst_n Input PIN_R17 5 B5_N0 2.5 V (default) 8mA (default)

RX1_SDA Bidir PIN_N15 5 B5_N0 2.5 V (default) 8mA (default) 2 (default)

rx_clk_n Input PIN_N18 5 B5_N0 2.5 V (default) 8mA (default)

rx_clk_p Input PIN_N17 5 B5_N0 2.5 V (default) 8mA (default)

rx_d_n[4] Input PIN_P1 2 B2_N0 2.5 V (default) 8mA (default)

rx_d_n[3] Input PIN_L3 2 B2_N0 2.5 V (default) 8mA (default)

rx_d_n[2] Input PIN_L5 2 B2_N0 2.5 V (default) 8mA (default)

rx_d_n[1] Input PIN_H1 1 B1_N0 2.5 V (default) 8mA (default)

rx_d_n[0] Input PIN_C1 1 B1_N0 2.5 V (default) 8mA (default)

rx_d_p[4] Input PIN_P2 2 B2_N0 2.5 V (default) 8mA (default)

rx_d_p[3] Input PIN_L4 2 B2_N0 2.5 V (default) 8mA (default)

rx_d_p[2] Input PIN_K5 2 B2_N0 2.5 V (default) 8mA (default)

rx_d_p[1] Input PIN_H2 1 B1_N0 2.5 V (default) 8mA (default)

rx_d_p[0] Input PIN_C2 1 B1_N0 2.5 V (default) 8mA (default)

sdi_ck_en1 Output PIN_J13 6 B6_N0 2.5 V (default) 8mA (default) 2 (default) 0 MHz

sdi_ck_sel0 Output PIN_H16 6 B6_N0 2.5 V (default) 8mA (default) 2 (default) 0 MHz

sdi_ck_sel1 Output PIN_N10 4 B4_N0 1.8 V 8mA (default) 2 (default) 0 MHz

tof_n Input PIN_M17 5 B5_N0 2.5 V (default) 8mA (default)

tof_p Input PIN_L16 5 B5_N0 2.5 V (default) 8mA (default)

TX1_SDA Bidir PIN_E17 6 B6_N0 2.5 V (default) 8mA (default) 2 (default)

TX2_SDA Bidir PIN_H17 6 B6_N0 2.5 V (default) 8mA (default) 2 (default) 0 MHz

tx_clk_n Output PIN_D1 1 B1_N0 2.5 V (default) 8mA (default) 2 (default)

tx_clk_p Output PIN_D2 1 B1_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_n[4] Output PIN_M1 2 B2_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_n[3] Output PIN_L1 2 B2_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_n[2] Output PIN_K1 2 B2_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_n[1] Output PIN_G1 1 B1_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_n[0] Output PIN_B1 1 B1_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_p[4] Output PIN_M2 2 B2_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_p[3] Output PIN_L2 2 B2_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_p[2] Output PIN_K2 2 B2_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_p[1] Output PIN_G2 1 B1_N0 2.5 V (default) 8mA (default) 2 (default)

tx_d_p[0] Output PIN_B2 1 B1_N0 2.5 V (default) 8mA (default) 2 (default)

vformat_n Input PIN_R1 2 B2_N0 2.5 V (default) 8mA (default)

vformat_p Input PIN_R2 2 B2_N0 2.5 V (default) 8mA (default)