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Altera_Forum
Honored Contributor
15 years agoProblème programmation Pin
Hello, For the passage of a signal, I use a pin in High Impedance, I declare it with : HZ : out std_logic_vector(11 downto 0); HZ<="ZZZZZZZZZZZZ"; My problem is with...
Altera_Forum
Honored Contributor
15 years agoWhat do you mean by perturbated ?
In your schema, the net_31 will not go higher than {3.3V + VLed}. If CPLD was not connected, your Led will emitting light if TS> {3.3V + VLed} if TS < {3.3V + VLed}, no source drives the net_31. The voltage level of net_31 would depend of Ts with R and design of the AOP (Operationnal Ampli), and it would be too sensitive. To resume : if ts=0, net_31 is unknown. Here, Led is functionning as a clamping Diode : is it exactly what you want ? (not sure) Check carefully your CPLD pins option. Try also / look at : - unused input tri-stated pin option in Quartus (if you are using Quartus) - inout pin - open drain pin