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Altera_Forum
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16 years ago

Powerup register reset values(again)

This is a quote from a previous post by vjAlter

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I just noted Altera posted a new knowledge base article, stating that the register power-up values are not 100% reliable: http://www.altera.com/support/kdb/so...12009_450.html <http://www.altera.com/support/kdb/solutions/rd06112009_450.html>

Isn't it a bit too late for issuing such a warning? I know that an external reset is considered good practice. But this is the firt time I see the warning, and I am sure during all these years, many cores were developed relying in the initial register values.

A more detailed elaboration of the problem would be nice. In some cases I used the PLL locked signal as an internal power-up reset source. Would be interesting to know if the PLL lock power-up counter is affected or not.

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The fact(now known) that the powerup register values can go wrong if an incoming clk is active during configuration makes it very difficult to rely on internally generated reset.

At times we do need to generate reset internally without relying on any input. The reset counter works in practice but who knows it is at the mercy of your incoming clk

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  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Thanks very much vjAlter and FvM,

    I now spotted my error of thinking.

    Basically what should have been said about reset release in various documents, therefore, is that a release near clk edge of launching register will affect the input of latching register if this implies a change of the signal state with respect to its state under reset.(never of launching register itself, this seems now obvious and common sense).

    Hence I don't forsee now difficulty in depending on the chip powerup state to create my own reset provided I take care. The counter example will do.

    The following example may be simpler 

    
 
D <= '1';
 
process
begin
wait until clk = '1';
    Q <= D;  -- starts as 0 if not optimised away
end process;
 
my_reset <= D and not Q;

    soon after configuration D is '1', while Q is '0' under chip reset

    any clk hits on the register will latch a '1' internally until release of chip reset.

    Thus I have one register(launch only, no problems).

    This in effect copies the chip reset to my reset which I will use to synchronise to other internal clks.

    Many thanks, it was fruitful finally.