Power-up sequence question about Cyclone 10 GX

Hi MinzhiWang,

Driving unpowered GPIO or transceiver pins can happen if external signals are applied before the FPGA's VCCIO or transceiver power rails are fully powered. The "driving unpowered GPIO" situation typically arises in scenarios where external devices drive signals into the FPGA before the FPGA's associated VCCIO (voltage supply for I/O banks) is powered up. To avoid this, ensure proper power sequencing, where VCCIO or transceiver rails are stable before external signals are active - If the FPGA's power supply is not properly sequenced, external devices might start operating and drive signals into the FPGA I/O pins while the FPGA's VCCIO is still ramping up or unpowered..

You can only combine and ramp up Group 3 power rails with Group 2 if both share the same voltage level and regulator as Group 2’s VCCPT.

Regards,

Fakhrul