Post-Fit Partition Export

Hi

I have a design, using RGMII-MAC on Cyclone-III, Quartus 11.0.

I have correctly constrained the PHY ports according to the source synchronous timing (http://www.alteraforum.com/alterawiki.com/uploads/e/ea/source_synchronous_timing.pdf). FPGA is receiver and phase shifts the incoming clock (Case 1).

I integrate my MAC in my top level project and it works. Timings are met.

When I change my top level design, timing is not met. So I want to lock my working version and export it to my new project, so that my MAC would work fine.

What I do:

1- Develop a working project.

2- Set the RGMII-MAC (and its PLL, inside it) as a design partition.

3- Set the RGMII-MAC (and its PLL, inside it) as a logic lock region.

4- Synthesize it again (This also works).

5- Export the RGMII-MAC partition as a .qxp file (Post-fit with routing).

6- Copy the whole project folder.

7- Delete all databases of copied project & all RGMII-MAC source files.

8- Run analysis & Elaboration.

9- Import the .qxp partition into the new project.

10- Synthesize.

After synthesis, the MAC does not work correctly. When I look at the chip planner, Placement of the PLL inside my MAC has changed and timings are not met either; i.e. the PLL of my working project is on a different tile from my new project, although I expected to be the same.

What's wrong with my procedure?

Should I change some Quartus settings?

I have SignalTap of my top ports of MAC. Does it make some problem?

Thanks