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Altera_Forum
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13 years ago

Porting source code to a new FPGA

Hi all

I would like to ask about porting a source code from old FPGA to a new one. Is it just compile or targeted its into a new FPGA and will be all done? Or how does it goes? Really need an advice here. I'm new to FPGA

Thanks and Regards

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    You will also probably have to redo some assignments, such as I/O standards and pins. What are the original and the new FPGAs?

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    Altera_Forum
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    Thanks Daixiwen for your replied.

    The original FPGA is from flex 6000 (epf6016ti144-3) and the new one is from cyclone IV (EP4CE6E22I7N). There is a differences in between the I/O (OLD = 117 : NEW =91).

    I'm scared that it'll be a problems. What is your opinion sir?

    Thanks and Regards
  • Altera_Forum's avatar
    Altera_Forum
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    It shouldnt be a problem (apart from the pinout) - but any megawizard files MAY have to be regenerated, depending on how they were targetted.

    What may cause you problems is oldschool design habits if any exist - like latches, internal tri-states or LCELLS to delay signals.
  • Altera_Forum's avatar
    Altera_Forum
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    As for the I/O, how many does your design actually use? As long as it is 91 or less it won't be a problem.

    Check also the voltages. You will of course need to redesign the PCB, but you will also need different supply voltages for the FPGA, and if you were using 5V I/O with the Flex, you will need to adapt those I/O to the maximum 3.3V supported by the Cyclone IV.
  • Altera_Forum's avatar
    Altera_Forum
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    Attached is my compilation results from the source code with current FPGA.

    Is there any flow or tips for me to do for porting this code to a new FPGA?

    Thanks and Regards
  • Altera_Forum's avatar
    Altera_Forum
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    you could probably just take a copy of this project and change the device and pinouts for a start.

  • Altera_Forum's avatar
    Altera_Forum
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    thanks sir. Do you know is there any core that exist for MSK (GMSK) modulation and demodulation for implement in FPGA?