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I've done some testing, and the SSRAM chip I am using is capable of pipelining arbitrary addresses for reads. Just thought to clear it up.
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Indeed, and as a matter of fact, some SSRAM datasheets show waveforms for back-to-back reads without bursting.
The question is then, why those chips has special support for bursting? Unless I miss something, you don't gain anything at all by using the ADV pin and the SSRAM internal burst counter.
Special bursting makes sense on RAM parts with multiplexed row and column lines. But here there is no such multiplexing, so I don't see what is the purpose of bursting.
Anybody?
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