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Altera_Forum
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14 years ago

port array declaration error

Hi, I'm trying to declare an array in my port entity. I have read some about on the web but I get an array declaration error. 


library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
--use ieee.std_logic_unsigned.all;
--use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
package mytypes is
	subtype data_ram_in is array(3 downto 0) of std_logic_vector (15 downto 0);
	subtype data_ram_out is array(3 downto 0) of std_logic_vector (31 downto 0);
end package mytypes;
--library STD;
--use STD.textio.all;
--library altera;
--use altera.all;
--use work.all;
use work.mytypes.all;
entity mult is
	port(
		clk		:in std_logic;
		reset		:in std_logic;
		mult_en 	:in std_logic;
	
		Data_a	:in data_ram_in;
		Data_b	:in data_ram_in;
		
		Data_out	:in data_ram_out
	);
end mult;
architecture beh of mult is
	S_a:in data_ram_in;
	S_b:in data_ram_in;
	S_out:in data_ram_out;
	
	begin
process (clk) 
	variable i : integer range 0 to 3;
	begin
	if ( rising_edge(clk) ) then
		if mult_en = '1' then
			for i in 0 to 3 loop
				s_out(i)<=Data_a(i)*Data_b(i);
			end loop;
		end if;
	end if;
end process;
end beh;

and I have this errors: 


Info: Found 0 design units, including 0 entities, in source file bufer.vhd
Error (10500): VHDL syntax error at mult.vhd(22) near text "array";  expecting an identifier ("array" is a reserved keyword), or a string literal
Error (10500): VHDL syntax error at mult.vhd(24) near text "array";  expecting an identifier ("array" is a reserved keyword), or a string literal
Error (10523): Ignored construct mytypes at mult.vhd(21) due to previous errors
Error (10523): Ignored construct mult at mult.vhd(35) due to previous errors
Error (10500): VHDL syntax error at mult.vhd(50) near text "S_a";  expecting "begin", or a declaration statement
Info: Found 0 design units, including 0 entities, in source file mult.vhd
Error: Quartus II Analysis & Synthesis was unsuccessful. 5 errors, 0 warnings
	Error: Peak virtual memory: 269 megabytes
	Error: Processing ended: Wed May 18 11:48:12 2011
	Error: Elapsed time: 00:00:20
	Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 7 errors, 0 warnings

It's a stupide error because I'm doing similar declaration than if it was not a port so I'm stucked.

Please if any one knows how to solve this erro I will be very thankfull.

Guillermo

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I make som changes: 

    
package mytypes is
	type data_ram_in is array(3 downto 0) of std_logic_vector (15 downto 0);
	type data_ram_out is array(3 downto 0) of std_logic_vector (31 downto 0);
end package mytypes;
--library STD;
--use STD.textio.all;
--library altera;
--use altera.all;
--use work.all;
--use work.mytypes;
entity mult is
	port(
		clk		:in std_logic;
		reset		:in std_logic;
		
	--	aux : in array(3 downto 0) of std_logic_vector (15 downto 0);
		
		mult_en 	:in std_logic
	
		Data_a	:in work.mytypes.data_ram_in;
	--	Data_b	:in work.mytypes.data_ram_in;
		
	--	Data_out	:in data_ram_out
	);
end mult;

    but now I have a strange error: 

    
Info: Found 0 design units, including 0 entities, in source file bufer.vhd
Info: Found 2 design units, including 1 entities, in source file correlator.vhd
	Info: Found design unit 1: Correlator-beh
	Info: Found entity 1: Correlator
Error (10482): VHDL error at mult.vhd(37): object "std_logic" is used but not declared
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
	Error: Peak virtual memory: 270 megabytes
	Error: Processing ended: Wed May 18 12:38:56 2011
	Error: Elapsed time: 00:00:20
	Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings

    What means std_logic is used but not declared??? I have the libraries, so I thinks must be something to do by my package, because if I don't used I don't have this error.

    Thanks again,

    Guillermo
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Eureka!!!!

    Ok, I made it work this way: 

    
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
--use ieee.std_logic_unsigned.all;
--use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
package mytypes is
	type data_ram_in is array(3 downto 0) of std_logic_vector (15 downto 0);
	type data_ram_out is array(3 downto 0) of std_logic_vector (31 downto 0);
end package mytypes;
library ieee;
use ieee.std_logic_1164.all;
--library STD;
--use STD.textio.all;
--library altera;
--use altera.all;
--use work.all;
use work.mytypes;
entity mult is
	port(
		clk		:in std_logic;
		reset		:in std_logic;
		mult_en 	:in std_logic;
	
		Data_a	:in work.mytypes.data_ram_in;
		Data_b	:in work.mytypes.data_ram_in;
		
		Data_out	:in work.mytypes.data_ram_out
	);
end mult;

    But can someone explain me why I need to put again the :

    library ieee;

    use ieee.std_logic_1164.all;

    after the package?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Have you tried to keep everything like in the original post and simply change "subtype" with "type" ?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    yes, is the firs thing I tried, and its when I get the std_logic error, but is solved in the way I show in the third post

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    That's should be correct.

    You must prefix

    library ieee; use ieee.std_logic_1164.all;

    to the package declarations, since it refers to std_logic types

    You must prefix the same to the entity declaration, since it directly uses std_logic, too,

    besides using mytypes.