port array declaration error

Eureka!!!!

library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
--use ieee.std_logic_unsigned.all;
--use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
package mytypes is
	type data_ram_in is array(3 downto 0) of std_logic_vector (15 downto 0);
	type data_ram_out is array(3 downto 0) of std_logic_vector (31 downto 0);
end package mytypes;
library ieee;
use ieee.std_logic_1164.all;
--library STD;
--use STD.textio.all;
--library altera;
--use altera.all;
--use work.all;
use work.mytypes;
entity mult is
	port(
		clk		:in std_logic;
		reset		:in std_logic;
		mult_en 	:in std_logic;
	
		Data_a	:in work.mytypes.data_ram_in;
		Data_b	:in work.mytypes.data_ram_in;
		
		Data_out	:in work.mytypes.data_ram_out
	);
end mult;