port array declaration error

I make som changes:

package mytypes is
	type data_ram_in is array(3 downto 0) of std_logic_vector (15 downto 0);
	type data_ram_out is array(3 downto 0) of std_logic_vector (31 downto 0);
end package mytypes;
--library STD;
--use STD.textio.all;
--library altera;
--use altera.all;
--use work.all;
--use work.mytypes;
entity mult is
	port(
		clk		:in std_logic;
		reset		:in std_logic;
		
	--	aux : in array(3 downto 0) of std_logic_vector (15 downto 0);
		
		mult_en 	:in std_logic
	
		Data_a	:in work.mytypes.data_ram_in;
	--	Data_b	:in work.mytypes.data_ram_in;
		
	--	Data_out	:in data_ram_out
	);
end mult;

but now I have a strange error:

Info: Found 0 design units, including 0 entities, in source file bufer.vhd
Info: Found 2 design units, including 1 entities, in source file correlator.vhd
	Info: Found design unit 1: Correlator-beh
	Info: Found entity 1: Correlator
Error (10482): VHDL error at mult.vhd(37): object "std_logic" is used but not declared
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
	Error: Peak virtual memory: 270 megabytes
	Error: Processing ended: Wed May 18 12:38:56 2011
	Error: Elapsed time: 00:00:20
	Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 0 warnings

What means std_logic is used but not declared??? I have the libraries, so I thinks must be something to do by my package, because if I don't used I don't have this error.

Thanks again,

Guillermo