PMA Direct Transceivers and ATX PLLs

Hi Dave,

Wow, I really do appreciate the detailed response! I also appreciate the offer to help dig in but I don't want to drag you into my issue. I was hoping someone had crossed this bridge before but I certainly don't want to create more work for you than I already have.

It may be a Quartus issue but looking at the nature of the problem, it seems like maybe it's correctly asserting the rules now where it might not have in the past. I don't think I'd used PMA direct xN before but it explicitly states in the documentation that you have to use that mode if you use the ATX PLLs. The errors and documentation seem to agree but there are enough gaps in the manual that I still might have a chance to get what I'm looking for. My concern is that the receiver CDR clocks might use some of the same clock distribution resources as the ATX PLL, making it so they can't be used together. I'll have to dig a little deeper on that one and if I come up with something, I'll post an example here.

I'm not sure if you've gotten any response on the service request but I had put one in a while back for the Transceiver Toolkit on Stratix IV and the official answer I got was that the it has limited (i.e. no) support beyond the design examples. I wanted to see if I could get the low latency phy working (CMU transceivers in PMA direct mode) and see if I could push some of the required components into hierarchical blocks to reduce the size of the Qsys design and increase the number of channels , neither of which I got working due to some low level errors. In the end, I just worked around it.

Thanks again,

Scott