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Honored Contributor
Honored Contributorplz help......Seqence recognizer error
`timescale 1ns/ 1ps module tb_seqrec; reg rnRESET, rCLK, rX; wire wZ; seqrec seqrec0(.nRESET(rnRESET), .CLK(rCLK), .X(rX), .Z(wZ)); always ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The text flagged in red is extraneous junk that does not belong there. What are you trying to do? --- Quote End --- oh. l just let you know verilog sentence sequence...https://alteraforum.com/forum/attachment.php?attachmentid=15536&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=15536&stc=1 in modelsim, l wrote this
