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Altera_Forum
Honored Contributor
Honored ContributorPLL usage
Hello all, I've noticed that many use PLL on the reference clock input even if they do not need to divide/multiply/shift this clock or do not have external clock to synchronize to the reference fr...
Altera_ForumHonored Contributor
Honored ContributorHi!
I have the following problem: I'm using a PLL of a StratixEP1S20 chip. I want to connect a PLL input to the output of an internal logic ( Clock Mux) and I get the following error message: ------------------------ Error: inclk0 port of PLL "Clocks_Delay:inst1|altpll0:inst9|altpll:altpll_component|pll" must be driven by a non-inverted input pin or, in a fast PLL, the output of a PLL Info: Input port INCLK[0] of node "inst1|altpll0:inst9|altpll:altpll_component|pll" is driven by Clock_MUX:inst|inst24 which is COMBOUT output port of Logic cell type node Clock_MUX:inst|inst24 -------------------- Is it ONLY possible to use PLL if the input signal is an external clock ? any comments! Kind regards JJ
