PLL reset input with Dynamic Phase Shifting

Hi Sree,

I probably didn't explain myself clearly. I was wondering if I have correctly generated the input reset of the PLL or if there are better ways to generate it, because in my project the timing requirement are not met for the input reset signal of the PLL.

I generated the PLL input reset with a counter that counts with the PLL reference clock. Instead, as you said too, I have generated the reset for the internal logic from the PLL lock signal. However, I had timing problems on the input reset signal. In particular, I used a PLL with the dynamic shifting interface activated. The timing violations is on the PLL input reset signal between the PLL reference clock domain and the one of clock used for the shifting interface.

I have never had a timing violation on the input reset of the PLL so I was wondering if I'm doing something wrong generating the input reset of the PLL in that way.

Best regards,

Dario