PLL reset input with Dynamic Phase Shifting

Hi Sree, thank you for the answer.

I have already generated the resets for the internal logic from the PLL lock signal, one for each clock domain. The timing issue is related to the input reset of the PLL. In other projects, I generated the input reset of the PLL with a counter (as described in my question) and there were no timing issues. The only difference here is the Dynamic Phase Shifting interface and indeed the timing issue is on the PLL input reset signal from the PLL reference clock domain to the Dynamic Phase Shifting interface clock domain.