Altera_ForumHonored Contributor17 years agoPLL reconfiguration with NIOS Hi I'm working with a cyclone III FPGA with a NIOS. That NIOS is going to reconfigure a PLL via its Avalon bus. My question is: Can the NIOS reconfigure a PLL generating the NIOS clock, and ...Show More
Altera_ForumHonored Contributor17 years agoThank you, I'm convinced. I am going to make the NIOS working on another fixed clock.
Recent DiscussionsDK-DEV-AGI027-RA QSPI Verification FailsCyclone 5 SoC FPGA Bank Supply PrerequisiteAGILEX 5 Migration issueTo INTEL - Request for Compliance Data from Analog Devices, IncArria 10 GX RX max intra-differential pair skew