I need two outputs from a single PLL of CYCLONE-III 3C16. Both the outputs are single-ended. One of outputs is 100MHz and the other is 120MHz-200MHz which will be dynamically configured through NIOS-II with variable phases. Those two outputs should be phase-synchronized. They are going to drive two separate loads of 50 ohm for impedance matching. I wonder if the PLL can provide up-to 30mA for each output in order to drive those two loads of 50 ohm . If not, please recommand practical solutions. Many thanks.

The maximum ratings say -25/+40 mA, also internal series termination isn't supported for the 3.3 V node. It mainly depends on the required receive level which isn't nebtioned in your post.

If you are driving a single load from each output consider using serial termination as it avoids the constant DC load of the parallel termination at the far side. In Cyclone III (and most other devices) series termination is easy.

Thanks. I did consider using series termination. However, it is not as good as parallel termination. If Cyclone III series termination is used, 2 extra I/Os, rup and rdn will be used or 2 external resistors will be used.

--- Quote Start --- However, it is not as good as parallel termination. --- Quote End --- In which regard? For LVTTL/LVCMOS outputs, parallel termination can't be used. Calibration resistors rup and rdn would be needed with calibrated termination only.

Thanks. One of clocks goes to a high-speed DAC in single-ended mode. In the single-ended mode, it needs 50ohm parallel termination for its best performance. The DAC could accept LVDS. The issue with LVDS from Cyclone-III FPGA is that a bank has to be configured as LVDS. As a result, we don't have enough I/O pins. The other clock (120MHz-200MHz) goes to the single-ended clock input of a device. Ideally, it is in 50ohm parallel termination. I can find up-to 166MHz clock drivers which are able to drive single-ended 50 ohm impedance with 2 inputs being synchronized.

PLL outputs to drive 50 ohm loads | Altera Community

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Altera_Forum
Honored Contributor
16 years ago
The VCCIO hasn't been mentioned. For some reason I expected 3.3V, but this is possibly wrong. However, there is effectively no difference in output driver operation between SSTL and other single ended standards. Both are choosing a driver impedance by enabling or disabling output transistors (from three or four available). Depending on the IO standard, it's either named drive strength or series termination.
Altera_Forum
Honored Contributor
16 years ago
FvM and jakobjones, thank you very much. The receivers in my application do NOT accept Vref and this is one of reasons SSTL Class I or HSTL Class I was not considered. At 3.3V level, as FvM said, FPGA is not able to source or sink enough current to a 50 ohm parallel termination. I am going to use 2 separate clock drivers to drive 2 50-ohm loads although there will be some differences of jitters and delays. The solution is to use a configurable PLL and dynamically adjust phase shift through NIOS-II.

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PLL outputs to drive 50 ohm loads

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