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Altera_Forum
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7 years ago

PLL of Cyclone V: 'reconfig_to_pll' bus description needed

Hi community, I'm working on a Project that has to be migrated from a Cyclone III to a Cyclone V FPGA. My problem is the PLL reconfiguration. Normally, the reconfiguration is processed by use...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Altera/Intel don't publish the details of that bus.

Can I ask why you don't want to use the PLL_RECONFIGURE IP - as is intended for PLL reconfiguration? You're clearly intending to do some redesign work in moving to Cyclone V from Cyclone III. Why not incorporate the PLL_RECONFIGURE IP and use the two bits of IP as intended? Controlling the PLL_RECONFIGURE IP is pretty straightforward...

Cheers,

Alex