PLL Lock range

The lock range can be determined using the following equations:

Fin(min) = Fvco(min) * N / M

Fin(max) = Fvco(max) * N / M

Fin = input frequency

Fvco = VCO frequency

Since M and N are constant for any PLL set up, and the Fvco min and max numbers are specified for the device family, you can solve for Fin min and max to determine your lock range.

Some exceptions though will clip the frequency, so your calculations may not always agree with Quartus II. These exceptions are based on the bandwidth selected. For example, the input frequency at the PFD must be at least 8 times the bandwidth (BW) frequency. That means Fin / N must be greater than 8x the BW. The bandwidth has a range reported by Quartus II as well, so this equation must be valid for the entire reported bandwidth range. The 8x BW rule must be applied to the highest BW value. If the rpt file says this:

Bandwidth = X MHz (Y MHz to Z MHz)

The highest BW is Z MHz (not X MHz). So with the 8x rule, it means the min PFD freq is Z x 8 = Fin(min) MHz.