PLL Implemantation

Hi,

I am testing out a design on the stratix II gx PCIe dev. board and found out the same warning during the fitter process

warning: pll "pll_25m:pll_25m|altpll:altpll_component|pll" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input

Based on the stratix II gx part no EP2SGX901508C3 pin information, bank 13 and 14 have no PLL. However, I see two differential clocks, 156.25 and 155.52 in to banks 14 (pin H7,H8) and 13 (pin P7,P8) respectively. I am using these clocks to generate 100 and 125 MHz respectively with PLL(s) and the synthesis complains about the inputs with the warning above for both PLL(s).

Apparently the board design did not use dedicated PLL inputs for the above clock inputs.

Please advise how to turn it off.

Thanks,

Fasahat