PLL Implemantation

Follow Rysc's suggestions about using the device pins that are dedicated for the PLL input and output functions. If you are getting the warnings with the dedicated pins, check whether you have a Global Signal setting on the clock signals in question.

I had a case where the PLL used a dedicated clock input pin that the Stratix II handbook said was associated with that PLL. Even with the correct combination of pin and PLL, a Global Signal setting caused the jitter warning. Forcing global usage with that setting resulted in an indirect route from the dedicated clock input pin to the global buffer to the PLL. Altera said that the PLL can't compensate for the additional delay caused by the global clock routing between the device pin and the PLL (note that this is not a problem for the internal destinations of a PLL being on global routing). With the Global Signal setting removed or set to off, the Fitter was allowed to use the dedicated routing from the dedicated pin to the PLL. If you have no Global Signal setting at all, the Fitter will probably use the global routing where it needs it and not use it for the pin-to-PLL connection. If you need the Global Signal setting on to force global usage for some things driven by the dedicated clock input pin, you can use a point-to-point setting to turn it off for just the path from the pin to the PLL.

I suspect the same situation can occur for a PLL output.

I asked Altera to add a statement about this cause of the warning to the help page for the message. Here's how the help looks in QII 7.2:

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PLL "<name>" input clock inclk[<number>] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input

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CAUSE: The specified PLL's input clock is not driven by a dedicated input pin. As a result, the input clock delay will not be fully compensated by the PLL. Additionally, jitter performance depends on the switching rate of other design elements. this can also occur if a global signal assignment is applied to the clock input pin, which forces the clock to use the non-dedicated global clock network.

ACTION: If you want compensation of the specified input clock or better jitter performance, connect the input clock only to an input pin, or assign the input pin only to a dedicated input clock location for the PLL. If you do not want compensation of the specified input clock, then set the PLL to No Compensation mode.

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