PLL Implemantation

I think we're mixing up names(which is understandable since Altera mixes them up since switching to TimeQuest and using their nomenclature.) The pin in the message is a top-level IO connection on your board. In TimeQuest, this is called a port, and the pin is the input/output connections of the actual PLL in the silicon. As Ben mentioned, the PLL pins in the silicon are dedicated.

But getting to those PLL pins from the user I/O(i.e. ports) can be done directly or circuitously. There are dedicated clock pins that drive the PLL directly, and each PLL has dedicated output pins to drive clocks off chip. (I'm not sure what device, but look at the handbook for more details). These are the ports you want to use. If you assign your I/O to anything else, then Quartus has to find a way from these I/O to/from the PLL, i.e. it uses generic routing resources that will add jitter. (I don't think the jitter will be huge though, just that it could be better. My biggest concern is the route to the PLL, since this route will not be compensated for by the PLL.)

So if your board isn't laid out, then please make these modifications. (You could use the pin-planner, but to be honest, just unassign these pins and I believe Quartus will choose the more direct path by default, assuming nothing else is using them). If you really need the best jitter, I believe the no-compensation setting of the PLL is best. The handbook should discuss this. I've never seen anyone use this because the jitter has always been really good with other compensation modes, but just pointing it out.