Altera_Forum
Honored Contributor
Honored ContributorPLL dedicated output - Cyclone III
This is not the first time when someone posts about this theme, but because it is not totally cleared I risk to repeat. Well, I got this warning message:
PLL "<name>" output port <name> feeds output pin "<name>" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance I have read several posts, and the CIII handbook, and as it says only the C0 can be dedicated clock. That is cleared. Because I don't have too much choice having CIII dev. board, the output is connected to HSMB# 39 pin, what is J22 on the FPGA. Of course I got the warning message. So, just because I was curious, I removed the pin assigment let the fitter choose the approriate pin. Nothing is changed I still get the warning message. Never mind... The question is guys (though as I told I don't have choice, so I'm just curious) really how can I find which pin is the# X PLL C0 (ded. clk out) on the device? How it is marked for example in the Pin Planner?
