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Altera_Forum
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13 years ago

PLL dedicated input pin?

Hello. In my design I want to use DDR2 external memory through ALTMEMPHY. The reference in external memory design guideline says I should trace the feeding clock to the dedicated pll input pin (av...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I've found a table, but it seem to be connections between GCLK networks and PLL outputs... still nothing about inputs :( .

I've just found another confusing thing about placing CK/CK# pins. It said:

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Place any differential I/O pin pair (DIFFIO) in the same bank or on the same side as the data pins. You can use either side of the device for wraparound interfaces. The first CK/CK# pair cannot be placed in the same row or column pad group as any of the DQ pins

--- Quote End ---

What does it mean? CK/CK# should not be placed in the same bank as DQ? Or it should not occupy same row/column of pins? But according to pin-out list there is no possible configuration to place all DQs and have at least one "free" row/collumn in same I/O bank:

http://s18.postimage.org/gwiu1tfbb/pin_assignment.png