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Altera_Forum's avatar
Altera_Forum
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13 years ago

PLL critical warning - 400MHz

Dear All,

I'm using this device - Cyclone IV - EP4CE22F17C6N

I created a PLL with 4 different clock outputs. (using Megafunction)

input f = 400MHz

output 1 = 100MHz with 90° shift

output 2 = 100MHz with 180° shift

output 3 = 100MHz with 280° shift

output 4 = 100MHz with 360°/0° shift

It was created without any issue.

Then I instantiated this file into my main verilog module. one of the main module's input is directly connected to pll's clock(400MHz).

I run the synthesis, I get the following error.

------------------------------------------------------------------------

Critical Warning: Cannot implement PLL <name of the ports> because the input clock of the PLL "xxx" uses I/O standard 2.5 V and has a frequency of 400 MHz. However, the device only supports a frequency up to 250 MHz.

------------------------------------------------------------------------

Initial it accepted for 400MHz but later it says it supports only upto 250MHz.

Could any one explain what is this?

Thanks!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    As far as I understand, 2.5V IO standard doesn't support 400 MHz by specification. You would want to refer e.g. to a LVDS input. The PLL Megawizard doesn't take account for IO constraints.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I think the megawizard does not check where the input signal comes from, i.e. logic, pin, etc. It just checks the clock speed and it seems to be ok for it (400MHz is pushing it a little). As long as the frequency is within certain bounds, it compiles the PLL OK. The synthesizer however does connectivity checks and that is probably where your design approach fails.

    I think you have two options here, either change the I/O standard of the dedicated clock input you are using, so you can use a 400MHz signal (if you use a dedicated clock input, which I hope you do) or you try to input a 40MHz signal and then use the PLL to beaf it up to 400MHz and do the phase shifts inclusive, if that is possible and you're not running of an external clock that is generated elsewhere.

    Otherwise you're out of luck, as far as I can tell.