Honored Contributor
Honored ContributorI think the megawizard does not check where the input signal comes from, i.e. logic, pin, etc. It just checks the clock speed and it seems to be ok for it (400MHz is pushing it a little). As long as the frequency is within certain bounds, it compiles the PLL OK. The synthesizer however does connectivity checks and that is probably where your design approach fails.
I think you have two options here, either change the I/O standard of the dedicated clock input you are using, so you can use a 400MHz signal (if you use a dedicated clock input, which I hope you do) or you try to input a 40MHz signal and then use the PLL to beaf it up to 400MHz and do the phase shifts inclusive, if that is possible and you're not running of an external clock that is generated elsewhere. Otherwise you're out of luck, as far as I can tell.
