Honored ContributorWe're using a Cyclone III LS FPGA in our design.
We're also using its internal PLL to shift a 120MHz input to a 240MHz clock. Does anyone know if there is any data from Altera regarding how PLL performance changes as the FPGA ages? Our customer has some question regarding how the waveform of the clock could change as time goes on. Thanks in advance!
Honored ContributorHi,
I assume this is worth a question for ALTERA support themselves, while based on the informations given, the PLL is realized digitally, thus I would be astonished if there wouldn't be mechanisms implemented to compensate any agig effects (if the realization structure is vulnerable to aging effects likewise analog PLL designs).Honored ContributorFPGA parameters slightly change over temperature and voltage, e.g. logic delay, but there's no effective aging. (Not considering exposure to huge amounts of ionizing radiation, e.g. in space instruments or a nuclear power plant which in fact causes degradation of semiconductors).
