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Altera_Forum
Honored Contributor
Honored ContributorPLL changes as it ages?
We're using a Cyclone III LS FPGA in our design. We're also using its internal PLL to shift a 120MHz input to a 240MHz clock. Does anyone know if there is any data from Altera regarding ho...
Altera_ForumHonored Contributor
Honored ContributorHi,
I assume this is worth a question for ALTERA support themselves, while based on the informations given, the PLL is realized digitally, thus I would be astonished if there wouldn't be mechanisms implemented to compensate any agig effects (if the realization structure is vulnerable to aging effects likewise analog PLL designs).
