PLL Auto Phase Adjust (Source Sync Outputs)

Well, looks like I'm not going to need an auto phase adjust at all. I've been optimizing the circuit a bit and inserted a DDIO element as an S-RAM clock repeater to have the fullspeed clock originate from an IOB register as well. With a 270 degrees phase shift for the dedicated PLL source on 200MHz, the S-RAM controller works perfectly now ;)

It is able to interact with the S-RAM on the starter kit at the full 200MHz speed with plenty slack left for the Tsu/Th requirements of the S-RAM. There are no delay cycles, except that for going from a read to a write there will be an extra dead cycle to avoid bus drive contention between the Cyclone and the S-RAM.