Please explain the following

I am having test bench vhdl using that I am doing simulation on quartus simulator tool to check the design and use the same kind of vector to test in real time. For that I need to give input address which is std logic vector.

At some point in test bench vhdl code I got like this

for I in 0 to 15 loop

BUS_ADDR_I <= CONV_STD_LOGIC_VECTOR(16#100#+I*2, 16);

....

.....

end loop;

I need to simulate this input address in waveform file How to decode this in to address bus?

Ex:

If it is like the following BUS_ADDR_I <= CONV_STD_LOGIC_VECTOR( 16#0210#, 16);

I'll drive address bus as 0x210