Forum Discussion
adrianf0
New Contributor
New ContributorPlatform Designer bug: AXI4-Lite Slave interconnection to AXI4 Master
According to the Platform designer documentation, the AMBA 4 AXI-Lite slave can be interconnected to AXI4 master. However, in such a case, rlast signal is not generated. The problem seems to be relat...
GuaBin_N_Intel
Contributor
ContributorAre you using burst or single transfer ?There is some requirement when using AMBA4 AXI-Lite slave https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-platform-designer.pdf, 3.13.5.1.
