Forum Discussion
Altera_Forum
Honored Contributor
16 years agoMany thanks FvM and kaz for your suggestions and for confirming my suspiscions... once I realized the expression could not be implemented as written your reorganization comment makes a lot of sense (although again the same restrictions regarding pipelining apply)... so after sleeping on it this is what I tried this morning (for anyone whose interested):
First I rewrote: A(n) = alpha*[X(n-1)-A(n-1)] + beta*[X(n)-A(n-2)] + X(n-2) as A(n) = {alpha*[X(n-1)]} - {alpha*[A(n-1)]} + {beta*[X(n)]} + {1*[Y(n-2)]} where Y(n-2) = {1*[X(n-2)]} - {beta*[A(n-2)]} - which can of course be pre-computed as long as it is done in 1 time step. A(n) can be completed in one time step by configuring a DSP Builder DSP Block with 4 multipliers and by deselecting the 'Register Output of the Multiplier' and also the 'Register Output of the Adder'. Y(n-2) can be implemented the same way, but with only 2 multipliers. The good news is that the output is now correct (as least according to the Simulink DSP Builder model). The downside is that is uses 24 DSP 18-bit Elements (remember that the bit width is 26). So does this revised implementation seem reasonable? If so, any ideas on how to reduced DSP resources used without reducing the bit width? Thanks again, Kurt