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Jayden's avatar
Jayden
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5 months ago

PIPE Direct Reset Release Sequence

Hello, I am debugging R-Tile Avalon Streaming FPGA IP for PCI Express in PIPE Direct mode on an Agilex 7 device. My goal is a custom PCIe/CXL soft controller. I was originally targeting x16, but I ...
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Venu's avatar
Venu
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2 hours ago

Hi Jayden​ Wincent_Altera​ 

I am also facing issue in reset release sequence. I am getting rx clock and rxelecidle first. after sometime, i am getting tx clock. once ln0_pipe_direct_pld_tx_clk_out_o is available , rx clock becomes 0. Once ln0_pipe_direct_pld_tx_clk_out_o is available, lnX_pipe_direct_tx_transfer_en_o is getting high. i am giving lnX_pipe_direct_pld_pcs_rst_n_i high. but i am not getting phy status high. it is 0 always. kindly help me out.  thank you for your time