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dalogan
New Contributor
New Contributorpin delay data 1SX280LN2F43I2LG
I am looking for the package pin delay data on the 1SX280LN2F43I2LG Stratix 10 FPGA for the High Speed I/O. I need that data to complete proper trace routing on the PWB. I also require any and all ha...
AminT_Intel
Regular Contributor
Regular ContributorHello Logan,
Do you mean you are looking for IO Timing or IOE delay? You can refer to page 112 to generate IO Timing: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10_datasheet.pdf
Thanks
daloganNew Contributor
New ContributorSorry I was away on holiday. The data I am looking for is not IO timing, but it is the delay from the ball of the bga to the pad on the die. I have worked with other vendors that provide this delay for the differential pairs for 10G and 25G interfaces. I then take this delay for the P-rail and N-rail of a differential pair and import into the CAD database which then accounts for the p-n skew and allows me to reduce . minimize the over p-n skew.
Thank you for your support
Dave Logan
