pin delay data 1SX280LN2F43I2LG

I review went to the links that were listed in the response. I reviewed the data sheet, gpio guidlines, and pin connections guidelines and found no documentation on the high speed I/O package delay / p-n skew information. I also have been in contact with te FPGA devlopment team at Nokia and asked them to provide "Report Datasheet" option in TimingQuest Analyzer. In reviewing that report there was no mention of P-N skew on the high speead interfaces (10G and 25G lanes) Please provide some documentation on the p-n skew for each high speed lane.

Thank you

Dave Logan