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Altera_Forum
Honored Contributor
Honored ContributorPhase modulation
The attached picture shows phase modulation of a clear clock by a sinusoidal signal.
Would you plz help me figure out what kind of circuit does this? I know there r generators that can generate this kind of signal but I want to know whats the basic -easiest- way to achieve such modulation. I also have some questions: 1. UI is the time of one period of the clock. Right? so 2/3 is chosen such that the maximum modulation doesnt result in losing a clock period or adding another one? 2. isnt the period supposed to be 1/fc (for the ideal clock)? why is it considered 2pi in this case? Thank you.2 Replies
Altera_ForumHi,
The sin(2*pi*fc*t) indicates the fundamental sinusoid component of the clock signal. This is a standard equation and the 2*pi allows the sine values to cycle around... The picture explains a clean clock jitter on the basis of two sinusoid phase modulation. You can see there is a clear relationship between clock jitter and the amplitude of the modulating sinusoid. In the digital domain you can reproduce that in a DDS circuit(Direct Digital Synthesiser) by generating the clock "sinusoid" component according to word value decided by a lut containing one cycle of the modulating sinusoid amplitude values). edit: alternatively, use altera NCO and set to phase modulation then pass the phase modulation value as variable input from the LUT. (altera NCO is an implementation type of DDS) Kaz- Altera_Forum
The diagram text is wrong. It says sin() but shows a square wave. The term jitter is used normally for an unwanted phase modulation.
I can't see, if the diagram is intended as an example to explain phase modulation or clock jitter analysis or if it shows a generated signal with specific parameters. Thus I can't comment the 2/3 modulation index, apart from confirming that it has to be below unity. The question, how to generate a similar signal may be answered different, depending on the required application parameters.
