Forum Discussion
New ContributorPFL core and PS configuration mode
Regular ContributorHi HT,
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf
Intel recommendation :When connecting quad SPI flashes in parallel, use identical flash memory devices with the same memory density from the same device family and manufacturer.
- MX25L12833E is Intel recommended flash and supports PFL but MX25L12833E is discontinued by Macronix and recommends MX25L12835F. We are not seeing major difference between MX25L12833F & MX25L12835F other-than Software Features & Technology.So PFL may work fine with flash.
- Yes, PFL will communication through SPI interface with the flash.the PFL logic in Intel CPLDs as a configuration controller for FPGA configuration. The PFL logic in the CPLD determines when to start the configuration process, read the data from the flash memory device, and configure the Intel FPGA in PS or FPP configuration scheme.
- The pages allow you to store designs for different FPGA chains or different designs for the same FPGA chain in different pages, The total number of pages and the size of each page depends on the density of the flash.Refer ug_pfl.pfd for mmore information
Let me know if you need any further assistance.
Best Regards,
Anand
New ContributorThanks for your explanation.
Still the paging is confusing for me. in Altera document, the flashes from Macronix (table 1 and 2) have not been listed with page mode capability but I can see they have the feature page read/write. do you think it is ok? can I save multiple configuration file in the chosen flash?
Many thanks,
Hamid
- AnandRaj_S_Intel
Hi Hamid,
The MX25L12833F & MX25L12835F flashes from Macronix are not tested by intel. We can not guarantee on performance.
But however i think read/write should work & you can program multiple configuration file.
Regards
Anand
