It worked in general, but I still have intermittent problems. Working at 37.6 MHz, some builds do not read data bits properly. Not completely (so that I can recognize data by the eye), but some bits are invalid. I have tried Quartus options for the pins:
// serial flash chip interface
(* altera_attribute = "-name FAST_OUTPUT_REGISTER ON" *)
output wire SF_DCLK,
(* altera_attribute = "-name FAST_OUTPUT_REGISTER ON" *)
output wire SF_NCS,
(* altera_attribute = "-name FAST_OUTPUT_REGISTER ON; -name FAST_INPUT_REGISTER ON" *)
inout wire SF_IO0,
(* chip_pin = "13", altera_attribute = "-name FAST_OUTPUT_REGISTER ON; -name FAST_INPUT_REGISTER ON; -name io_maximum_toggle_rate 0" *)
inout wire SF_IO1
it helps somehow, but not always. I can not release unreliable project, and can not lower the operating frequency. I will have to drop using this chip for this project if will not find suitable solution or mitigate the problem.
Unfortunately there're ignored assignments in the Fitter section:
Fast Input Register -- SF_IO0 -- ON -- Compiler or HDL Assignment
Fast Input Register -- SF_IO1 -- ON -- Compiler or HDL Assignment
however I feed registers with this bidir input:
r_serial_flash_output_data[31:0] <= { r_serial_flash_output_data[29:0], SF_IO1, SF_IO0 };
As I understand with the current setup Quartus fits output register to the nearby cell, but input register may appear at distance causing timing problem.
What can I do not force Quartus putting input registers into the cell nearby to the pin? What is wrong in my setup forcing Quartus ignoring fast input register assignment?
Please help me.
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