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rshal2's avatar
rshal2
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Peloader hang in clock calibration

Hello, The following function get hang in my application. I can't knows exactly why, because preloader is getting compiled with debug information (Is there a way to Turn it off)? What I see is: ...
FawazJ_Altera's avatar
FawazJ_Altera
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello sir,

The pll input clock should be 25MHz based on our reference design. Anything below or above might not function properly since there was no test achieved to verify. Is it possible to change the PLL input clock on your board (to make it 25MHz)?

Thank you

  • rshal2's avatar
    rshal2
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Hi,

    The issue seems to be solved.

    The real problem was that in platform designer HPS clock was set as 25M, while the real clock was 50M.

    On changing qsys hps clock to 50M , the issue been solved.

    Thanks