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Abhi_kr's avatar
Abhi_kr
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9 months ago

PCIe root port BFM simulations for Cyclon10 GX device is taking more time compared to Cyclon 5

I am using the PCIe Root Port BFM generated for the Cyclone 10 GX device in my simulation environment. I've noticed that the simulations are significantly slower compared to those using the Root Port...
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Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
9 months ago

Hi,


First and foremost

  1. Can I know what design that you are using , the design generated from IP catalog ? or this is own custom design
  2. May I know, how long the simulation time ?
  3. Do you include whole signal in the simulator or certain signal only , If you do not need to see the whole signal, I suggest to include partial signal, then it will better improve the simulation completed time.
  4. What is the simulator that you are using ? Based on my experience , in certain IP for Cyclone 10 for etc emif IP, the Synopsys simulator is fastest compare to mentor and modelsim, perhaps you can try that as well.


I would like to know if there are any generics or settings available in the Root Port BFM files that could help improve simulation speed.

>> You may refer to the guide there https://www.intel.com/content/www/us/en/docs/programmable/683686/20-4/setting-up-simulation.html

>> if there is anything unclear, please get back to me.


Regards,

Wincent_Altera


Abhi_kr's avatar
Abhi_kr
Icon for New Contributor rankNew Contributor
9 months ago

Hi,

  1. I am using the root port BFM and associated files generated from the IP catalogue, but i am using my own PCI user application (Design files are not from the IP catalogue).
  2. For the initial PCIe configuration i.e. accessing the PCIe registers and configuring the MSI registers taking almost 173.448 us (about 15 minutes in real time) . But after this i am doing some DMA operation specific to my design which was taking around .5 to 1hr in the older PCIe root port BFM environment (Cyclon 5) . But for the new root port BFM files it is takin 4 to 5 hrs. The deign files are all the same. Only the root port BFM files got updated.
  3. I am adding only the required signals on the simulations.
  4. I am using the Questa Sim 2023.2 version from mentor.

Also as mentioned in the first post, I would like to know why the clock is behaving like that.

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    9 months ago

    Hi Abhi,

    Also I have noted that clock in for the driver downstream module is going to unknown state in between the simulation.
    >> Can you please provide me the full clock name ?
    >> or any printscreen will do. I might need time to check on this behaviour

    Regards,

    Wincent_Altera