PCIe Link training

In our system FPGA 5CGXFC7D6F27I7N and CPU TMS320x are connected via PCIe x2 GEN1. During link training LTSSM goes through such states:

• 0 Detect.Quiet

• 1 Detect.Active

• 2 Poling.Active

• 3 Polling.Compliance

• 2 Polling.Active

• 4 Polling.Configuration

• 6 config.Linkwidthstart

• 7 Config.Linkaccept

• 9 Config.Lanenumwait

• 8 Config.Lanenumaccept

• A Config.Complete

• B Config.Idle

• F L0

But sometimes, for no apparent reason, it gets stuck at Polling.Compliance state. Can we somehow ban transition to this state ? For example, with the help of HIP test_in bus