PCIe interface in Cyclone IV

Figure 1-1 and 1-2 at the following device handbook link show which transceiver blocks have the PCIe Hard IP. You can visually locate these blocks easily in Pin Planner tool within Quartus II. Make sure to place Lane 0 on physical channel 0 of the block, one to one, etc.

http://www.altera.com/literature/hb/cyclone-iv/cyiv-52001.pdf#page=2

Hi,

Are you using the soft IP or the hard IP? If using the Cyclone IV GX, I'd recommend using the hard IP. Then you'll be using all those transceiver pins you mentioned. I'd recommend you start with this Altera PCIe reference design "PCI Express to DDR2 SDRAM Reference Design". Read the User Guide for this ref des and also the Altera PCIe Compiler User Guide to get started. You don't have to bother with the PCI/PCIe spec for now. See the link below for more details.

http://sites.google.com/site/ednalabs/project/fpga/tips/pcie-design-with-altera

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hi,

I want to configurethe PCI express interface of Cyclone IV GX (EP4Cgx150CF23C7N) FPGA. Can I use any of the transceiver pins (eg. GXB_RX, GXB_TX, etc.) or are there any specific pins? I am not able to find it in the handbook.

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